1. Field of the Invention
The present invention relates to an ATM network time management method suitably used for a high-speed broadband network such as an ISDN.
2. Description of the Prior Art
Recently, an ATM (Asynchronous Transfer Mode) network has been developed as a technique of realizing multimedia services. In the ATM network, with an increase in cell delay variation (CDV), the peak cell rate increases, and a traffic with a high burstiness may be included. As a result, the utilization efficiency of the network decreases. For this reason, cell flows must be equalized by adding an optimum delay to each cell at each connection.
In algorithm computation for this equalization, the ideal transmission time of an arrival cell is calculated on the basis of the arrival time of a preceding cell. This operation demands time management for determining the relationship in magnitude between time parameters required for the algorithm computation by referring to a timer value.
For example, such a technique is disclosed in Japanese Unexamined Patent Publication No. 4-329733. According to this reference, information indicating the time at which the first cell arriving after a measuring/monitoring operation was started is stored in a memory at each node in the ATM network. If a predetermined measurement allowable time elapses in the interval between this time and the time at which the next cell having the same identifier as that of the first cell arrives, the occurrence of an abnormality is determined, and measurement is performed again.
With this arrangement, it is unnecessary to provide a register with every VPI or VCI. A reduction is circuit size can therefore be attained. In addition, even if a cell arrives at a time beyond the physical arrival time interval storage limit of the memory, no erroneous cell flow rate information is output, and accurate cell flow rate information can be provided.
In the above conventional time management method, time management is performed on the basis of absolute times, and hence requires a timer length based on the maximum operation time after the time the power supply is turned on. The bit length of the timer counter becomes therefore long, resulting in an increase in circuit size. As the circuit size increases, the processing speed decreases.
The present invention has been made in consideration of the above situation, and has as its object to provide an ATM network time management method which can increase the processing speed by reducing the circuit size.
In order to achieve the above object, according to the basis aspect of the present invention, there is provided an ATM network time management method of performing a shaping operation to equalize cell flows by generating an arrival time of a cell on the basis of arrival intervals of input cells and by adding an optimum delay to the arrival time, thereby obtaining an ideal transmission time to, comprising preparing a flag indicating whether a value of a timer counter for generating an arrival time of a cell on the basis of arrival time intervals of input cells has exceeded a maximum timer cycle value, and performing the shaping operation by managing the arrival time of the cell with reference to a relative time in accordance with a state of the flag.
In the basic aspect, according to the form of the flag, the flag comprises a first flag indicating whether a next TET value obtained by adding a minimum cell interval Ts to a theoretical transmission time TET has exceeded a maximum timer value and a next timer cycle has been started, and a second flag indicating whether a cell arrival time ta of a cell has come in a cycle longer than the minimum cell interval Ts, and has exceeded the maximum value of the timer.
According to the form of the flag, the first and second flags are prepared in units of VPI/VCI numbers of input cells.
According to the form of the flag, the method further comprises setting the first flag to xe2x80x9c0xe2x80x9d when the next TET value obtained by adding the minimum cell interval Ts to the theoretical transmission time TET has exceeded the maximum timer value, and the next timer cycle has been started, and setting the first flag to xe2x80x9c1xe2x80x9d when the next TET value has not exceeded the maximum timer value, and the next timer cycle has not been started, setting the second flag to xe2x80x9c1xe2x80x9d when the cell arrival time ta of the cell has come in a cycle longer than the minimum cell interval Ts, and has exceeded the maximum value of the timer, and setting the second flag to xe2x80x9c0xe2x80x9d when the cell arrival time ta has not come in a cycle longer than the minimum cell interval Ts, and has not exceeded the maximum value of the timer, performing a normal shaping operation when both the first and second flags are set to xe2x80x9c0xe2x80x9d, setting the theoretical transmission time TET to be equal to the arrival time ta of the cell, and setting the ideal transmission time to to be equal to the arrival time ta of the cell when the first and second flags are respectively set to xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, performing a shaping operation by correcting the theoretical transmission time TET according to TET=TET+maximum timer value t when the first and second flags are respectively set to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, and performing processing for an abnormal state when both the first and second flags are set to xe2x80x9c1xe2x80x9d.
According to the basic aspect, a timing at which the flag is updated can be shifted in units of VPI/VCI numbers.
In the present invention, there are provided flags indicating on the basis of the arrival intervals of input cells whether the timer counter value of the timer counter for generating the arrival time of a cell has exceeded the maximum timer cycle value, and a shaping operation is performed by managing the arrival time of the cell with reference to a relative time in accordance with the states of these flags. Therefore, the bit length of the timer counter can be decreased, and the circuit size can be reduced as compared with a case in which time management is performed on the basis of absolute times. In addition, since the bit length of the timer counter can be decreased, the number of adders, subtracters, and the like can be decreased. Consequently, the computation time can be shortened to realize high-speed processing.
The above and many other objects, features and advantages of, the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principles of the present invention are shown by way of illustrative example.